EN0-001 Practice Exam Questions with Answers ARM Accredited Engineer Certification

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FIQ

Undefined Instruction

Parity

0xAA.

0x00.

0xBB.

Unpredictable.

Protect memory.

Improve performance.

Implement virtual memory,

Ensure correct ordering of memory operations.

Translates virtual addresses to physical addresses

Generates parity information to detect soft errors in memory

Performs access permission checks

Permits the system to be divided into secure and normal worlds, through the use of ARM's TrustZone technology

A dedicated real-time clock to provide the total cycle count

Use of the divide-by 64 counting option to avoid an overflow of the cycle counter

Use of the overflow interrupts, to extend the range of the built-in 32-bit counter

Modification of the application software being profiled, to insert timestamps at regular intervals

2

16

32

256

TCMs are a part of only L1 cache system

TCMs are a part of only L2 cache system

TCMs are part of both L1 & L2 cache systems

TCMs are not part of either L1 or L2 cache systems

Memory read instructions, and memory write instructions

Architecturally executed instructions, and instruction fetches causing a cache line refill

Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

Memory read or write operations causing a cache access, and architecturally executed instructions

Hard floating-point linkage

Soft floating-point linkage without floating-point hardware

Hard floating-point linkage with optimization for space

Soft floating-point linkage with floating-point hardware

BLX

RFEFD

SRSFD

SVC

An external DMA engine modifies data in a region of data memory which is already cached by the processor

An external agent needs to read data which has been modified by the processor in a cacheable memory region

Debugger reads data from a shared, cacheable memory location

One core modifies data in a shared cacheable memory region

0

4

8

15

Thumb is a hybrid 16/32-bit instruction set

No Thumb instructions can be conditionally executed

Thumb code is always slower than the equivalent ARM code

Some routines take more instructions in Thumb code than in the equivalent ARM code

The Thumb instruction set can access the Advanced SIMD "NEON" instructions

Thumb code is always more power-efficient than equivalent ARM code

Both IRQs and FIQs are enabled

Both IRQs and FIQs are disabled

IRQs are disabled and FIQs are enabled

IRQs are enabled and FIQs are disabled

Cortex-A8

Cortex-M3

Cortex-R4F

Cortex-A9 MPCore

The time spent waiting for I/O operations

The time taken to download the program via the debugger

The time taken for memory accesses

The time taken for the CPU to execute instructions

The time taken to compile the source code

The time taken to perform instruction tracing

±32MB

±4MB

±12KB

±4KB

0x11223344

0x44332211

0x22114433

0x33441122

ID0-ID7

ID0-ID15

ID0-ID31

ID0-ID63

Cache control operations

Address translation operations

Debug control and status information

Architecture feature ID registers

Replace all functions which use semi-hosting

Locate the stack in an area of RAM

Set the locale variable appropriately

All functions in the standard library must be rewritten

Inactive to Active

Inactive to Pending

Active to Inactive

Pending to Active

Shareable Memory

Snoop Control Unit

Private Memory Region

Level 2 Cache Controller

0x0

0xF

0xFF

0xFFFFFF

VFP

The System Control Coprocessor (CP15)

Support for memory barriers

A Memory Protection Unit conforming to the PMSA

Allow an external interrupt to interrupt an SVC handler

Reduce response time for higher priority interrupts

Allow an interrupt handler to be relocated in memory

Avoid the need for an interrupt handler to use a stack.