EN0-001 Practice Exam Questions with Answers ARM Accredited Engineer Certification

Instruction cache clean only

Instruction cache invalidate only

Data cache clean and instruction cache invalidate

Data cache invalidate and instruction cache invalidate

The memory system has visibility of the security status of all accesses, and will reject all Non-secure accesses to Secure memory

Secure memory contents are encrypted, and cannot be decrypted by Non-secure software

The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set

The MMU generates an abort on accesses to Secure memory performed by Non-secure software

200

201

204

208

Sharing data with another thread running on the same core

Sharing data with another process running on the same core

Sharing data with an external device

Sharing data with another CPU in an SMP system

Cache Size

Clock Speed

Program size

Numbers of instructions executed

ROM

Heap

Cache

Registers

Stack

The loop must fit into two cache lines

The loop must only contain forward branches

Only integer arithmetic can be used

All variables must be held in registers

It has lower capacity

It is quicker to access

It is always available

It is easy to share with other devices

Influenced by breakpoints.

Intrusive on normal processor operation.

Inaccurate regarding code execution history.

Not intrusive on normal processor operation.

Compiling exception handlers

Specifying a Thumb-capable processor (e.g. -cpu=Cortex-A9)

Enabling Thumb code generation on the command line (--thumb)

Configuring the compiler for maximum code density (-Ospace)

Cache support

Privileged execution

The ARM instruction set

Virtual memory support

R0=0x100, R1 =0x1000

R0=0x100, R1=0x1002

R0=0x101, R1=0x1002

R0=0x101. R1=0x1003

None

Always one

Always three

One or more depending on optimization level

Coherency

Pre-fetch

Eviction

Allocation

Interrupt from a private peripheral to a processor

Interrupt from a processor to a private peripheral

Interrupt from a shared peripheral to a processor

Interrupt from a processor to a shared peripheral

Interrupt from a private peripheral to a shared peripheral

Interrupt from a shared peripheral to a private peripheral

Tracing using Embedded Trace Macrocell (ETM)

Halt mode debugging

Monitor mode debugging

Using the Performance Monitor Unit

Reading the link register (R14)

Reading data from the user stack

Changing from ARM state to Thumb state

Changing the interrupt mask bits (A, I, F) in the CPSR

Speculative accesses might waste energy

Speculative accesses might reduce performance

Speculative accesses might cause unwanted cache coherency traffic

Speculative accesses might cause undesired system state changes

It traps writes to the memory containing the vector table

It provides additional resources for debugging exception handlers

It provides configurable exception priorities on an ARM processor

It provides an improved mechanism for an application to handle exceptions

All processors have the same view of memory

An even number of processors is included

All processors run in the same power state

All processors switch between operating system tasks in lock-step

A dual-core Cortex-A9 processor

A Cortex-R4 processor with a Cortex-M3 system controller

A Cortex-A8 processor with a graphics processing unit (GPU)

A uni-core Cortex-A5 processor with a digital signal processor (DSP)

Inactive to Active

Pending to Active

Active to Inactive

Active to Pending

bits [5:0]

bits [7:2]

bits [15:10]

bits [31:26]

Allow an external interrupt to interrupt an SVC handler

Reduce response time for higher priority interrupts

Allow an interrupt handler to be relocated in memory

Avoid the need for an interrupt handler to use a stack.

R2 = 0xBB

R2 = 0xCB

R2 = 0xAA

R2 = 0xCC

Writes dirty data cache lines to memory

Reloads dirty data cache lines from memory

Speculatively preloads data into the cache

Writes dirty data cache lines to memory and marks those lines as invalid

Produce a binary object that will run on processors based on any architecture.

Mix different source languages within the same source file and compile with a single tool.

Run code written for one processor on a processor based on a different architecture.

Compile target code using a computer based on a different architecture.

Register an interrupt which is triggered when the counter overflows

Count the events using a 64-bit VFP register

Allow one event type to use concatenated counter registers

Poll the event counter, resetting it when the counter is close to overflowing

Accessing a large memory device consumes less power than accessing a small one

A series of non-sequential accesses is more efficient than a series of sequential accesses

Increasing the size of the cache will always reduce power consumption for a given application

Storing frequently used data in Tightly Coupled Memory will reduce power consumption

A single-threaded application needs to manage two separate UART peripherals

Two independent threads running on a single processor both need to access a single UART

In a dual-core system, a UART is accessed by a single thread running on one of the processors

In a dual-core system, processor A needs to access UART A and processor B needs to access UART B

Use an ETM instruction trace profiler, which outputs information about the program as it runs

Add some serial logging to the software, which outputs information about the program as it runs

Add a new interrupt handler, which is triggered off a timer, and dump information about the interrupted process

Use a JTAG sample-based profiler, which periodically halts the CPU, and dumps information about the interrupted process

0x11223344

0x44332211

0x22114433

0x33441122

It must start executing from RAM

RAM must be initialized before reset

Exception handlers must execute from ROM or flash memory

It must not execute semihosting SVC or BKPT instructions

When executing the software using a simulation model

When the processor is a Cortex-R4

When instruction tracing is enabled

When the processor is not executing instructions from cache

R0

R1

R2

R3

Additional quadword registers

Support for double precision floating-point arithmetic

Fused Multiply-Accumulate (Fused MAC) instructions

Support for polynomials

Encrypting sensitive data on a network

Preventing interrupts from being received by a CPU

Preventing unauthorized access to an ARM powered device

Protecting a critical section or data structure from concurrent access

Thumb is a hybrid 16/32-bit instruction set

No Thumb instructions can be conditionally executed

Thumb code is always slower than the equivalent ARM code

Some routines take more instructions in Thumb code than in the equivalent ARM code

The Thumb instruction set can access the Advanced SIMD "NEON" instructions

Thumb code is always more power-efficient than equivalent ARM code

Ir

r0

CPSR

SCTLR

PC=LR

PC=LR44

PC=LR-4

PC=LR-8

The Thumb-2 instruction set

NEON

Integer division instructions

A memory management unit

0xAA.

0x00.

0xBB.

Unpredictable.

Protect memory.

Improve performance.

Implement virtual memory,

Ensure correct ordering of memory operations.

Inactive

Active

Pending

Edge-triggered

Cortex-A8

Cortex-M3

Cortex-R4F

Cortex-A9 MPCore

Level 1

Level 2

Level 3

Level 4

A simpler branch instruction can be used.

Decrementing variables uses less power than incrementing them.

The decrement and branch operations can be encoded as a single instruction.

The loop termination condition check can be integrated into the subtract operation.

Halting a single user thread in an embedded Linux system is not possible

Use the Linux kernel printk() function to output messages to the console

Connect a Linux-aware JTAG debugger to the target, which allows single-stepping of the code

Connect a debugger running on an external host device to an instance of gdbserver running on the target, using Ethernet

Memory mapping

Semihosting

Polling

Virtual I/O

Supervisor Call

FIQ

Undefined Instruction

Parity

It is fetched.

It is decoded.

It is executed.

It writes back its results.

Unaligned accesses may take more cycles to execute than aligned accesses

Unaligned loads and stores are necessary for accessing fields in packed structures

A program compiled using unaligned accesses can be safely executed on all ARMv7-A devices

If the relevant control register setting is enabled all loads and stores can function from unaligned addresses

Unaligned accesses can only be made to Normal memory

Before executing code that uses the NEON instruction set

Before handling an interrupt request raised by an external device

Before checking the status of a semaphore

Before reading cacheable memory that has been written to by an external bus master

Cycle-accurate simulation of the CPU.

Instruction-accurate simulation of the CPU.

Simulation of user-defined memory-mapped peripherals.

Cycle-accurate simulation of the cache and memory system.

Base address of the heap must be the same as the initial stack pointer.

Stack pointer must be 8-byte aligned.

Heap must be in external RAM.

Initial stack pointer must be the lowest addressable memory location.

6 bits

7 bits

9 bits

15 bits

1 multiplication

4 multiplications

16 multiplications

64 multiplications

8 bits

16 bits

32 bits

64 bits