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  • Exam Name: ARM Accredited Engineer
  • Last Update: Apr 23, 2024
  • Questions and Answers: 210
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EN0-001 Practice Exam Questions with Answers ARM Accredited Engineer Certification

Question # 6

Which of the following is an external exception?

A.

Supervisor Call

B.

FIQ

C.

Undefined Instruction

D.

Parity

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Question # 7

Consider the following piece of code:

EN0-001 question answer

The value of r7 after execution of the above piece of code is:

A.

0xAA.

B.

0x00.

C.

0xBB.

D.

Unpredictable.

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Question # 8

The purpose of a translation lookaside buffer (TLB) is to:

A.

Protect memory.

B.

Improve performance.

C.

Implement virtual memory,

D.

Ensure correct ordering of memory operations.

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Question # 9

The Memory Protection Unit (MPU) of Cortex-R4 performs which of the following tasks?

A.

Translates virtual addresses to physical addresses

B.

Generates parity information to detect soft errors in memory

C.

Performs access permission checks

D.

Permits the system to be divided into secure and normal worlds, through the use of ARM's TrustZone technology

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Question # 10

Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?

A.

A dedicated real-time clock to provide the total cycle count

B.

Use of the divide-by 64 counting option to avoid an overflow of the cycle counter

C.

Use of the overflow interrupts, to extend the range of the built-in 32-bit counter

D.

Modification of the application software being profiled, to insert timestamps at regular intervals

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Question # 11

An Advanced SIMD intrinsic has the prototype:

uint8xl6x2_t vld2q_u8 (uint8_t const * ptr);

How many bytes does this intrinsic load from memory?

A.

2

B.

16

C.

32

D.

256

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Question # 12

Which of the following best describes the relationship between Tightly Coupled Memories (TCM), Level 1 (L1) and Level 2 (L2) cache memory systems?

A.

TCMs are a part of only L1 cache system

B.

TCMs are a part of only L2 cache system

C.

TCMs are part of both L1 & L2 cache systems

D.

TCMs are not part of either L1 or L2 cache systems

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Question # 13

Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?

A.

Memory read instructions, and memory write instructions

B.

Architecturally executed instructions, and instruction fetches causing a cache line refill

C.

Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

D.

Memory read or write operations causing a cache access, and architecturally executed instructions

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Question # 14

The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?

A.

Hard floating-point linkage

B.

Soft floating-point linkage without floating-point hardware

C.

Hard floating-point linkage with optimization for space

D.

Soft floating-point linkage with floating-point hardware

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Question # 15

When using an Operating System, which instruction is used by user code to request a service from the kernel?

A.

BLX

B.

RFEFD

C.

SRSFD

D.

SVC

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Question # 16

Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?

A.

An external DMA engine modifies data in a region of data memory which is already cached by the processor

B.

An external agent needs to read data which has been modified by the processor in a cacheable memory region

C.

Debugger reads data from a shared, cacheable memory location

D.

One core modifies data in a shared cacheable memory region

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Question # 17

How many bytes of stack are needed to pass parameters when calling the following function?

int foo( short arg_a, long long arg_b, char arg_c, int arg_d )

A.

0

B.

4

C.

8

D.

15

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Question # 18

Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)

A.

Thumb is a hybrid 16/32-bit instruction set

B.

No Thumb instructions can be conditionally executed

C.

Thumb code is always slower than the equivalent ARM code

D.

Some routines take more instructions in Thumb code than in the equivalent ARM code

E.

The Thumb instruction set can access the Advanced SIMD "NEON" instructions

F.

Thumb code is always more power-efficient than equivalent ARM code

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Question # 19

In the CPSR, 1=0 and F=1. Which of the following is TRUE in this case?

A.

Both IRQs and FIQs are enabled

B.

Both IRQs and FIQs are disabled

C.

IRQs are disabled and FIQs are enabled

D.

IRQs are enabled and FIQs are disabled

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Question # 20

Which of the following processors includes a Generic Interrupt Controller as a standard component?

A.

Cortex-A8

B.

Cortex-M3

C.

Cortex-R4F

D.

Cortex-A9 MPCore

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Question # 21

In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)

A.

The time spent waiting for I/O operations

B.

The time taken to download the program via the debugger

C.

The time taken for memory accesses

D.

The time taken for the CPU to execute instructions

E.

The time taken to compile the source code

F.

The time taken to perform instruction tracing

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Question # 22

In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?

A.

±32MB

B.

±4MB

C.

±12KB

D.

±4KB

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Question # 23

Assume a Big-Endian (BE) memory system with the following memory contents.

Byte Address Contents

0x100 0x11

0x101 0x22

0x102 0x33

0x103 0x44

If R5 = 0x100, what are the contents of R4 after performing the following operation?

LDR R4, [R5]

A.

0x11223344

B.

0x44332211

C.

0x22114433

D.

0x33441122

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Question # 24

In the Generic Interrupt Controller (GIC) architecture, which of the following ID numbers are reserved for interrupts that are private to a CPU interface?

A.

ID0-ID7

B.

ID0-ID15

C.

ID0-ID31

D.

ID0-ID63

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Question # 25

In a Cortex-A9 processor, CP14 system control registers are used for:

A.

Cache control operations

B.

Address translation operations

C.

Debug control and status information

D.

Architecture feature ID registers

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Question # 26

When developing a product using the standard ARM C library, what is the minimum effort required to re-target all platform-specific functions in the library?

A.

Replace all functions which use semi-hosting

B.

Locate the stack in an area of RAM

C.

Set the locale variable appropriately

D.

All functions in the standard library must be rewritten

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Question # 27

When an interrupt service routine reads the Generic Interrupt Controller (GIC) Interrupt Acknowledge Register, what state transition occurs for that interrupt ID?

A.

Inactive to Active

B.

Inactive to Pending

C.

Active to Inactive

D.

Pending to Active

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Question # 28

The Cortex-A9 MPCore processor contains a hardware block whose function is to maintain data cache coherency between cores. What is the name of this block?

A.

Shareable Memory

B.

Snoop Control Unit

C.

Private Memory Region

D.

Level 2 Cache Controller

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Question # 29

What is the maximum value of the immediate field in an ARM SVC instruction?

A.

0x0

B.

0xF

C.

0xFF

D.

0xFFFFFF

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Question # 30

Which of the following is an optional extension to the ARMv7-A architecture?

A.

VFP

B.

The System Control Coprocessor (CP15)

C.

Support for memory barriers

D.

A Memory Protection Unit conforming to the PMSA

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Question # 31

A re-entrant interrupt handler would typically be used to:

A.

Allow an external interrupt to interrupt an SVC handler

B.

Reduce response time for higher priority interrupts

C.

Allow an interrupt handler to be relocated in memory

D.

Avoid the need for an interrupt handler to use a stack.

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