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  • Exam Name: ARM Accredited Engineer
  • Last Update: 22-Jun-2024
  • Questions and Answers: 210
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EN0-001 Questions and Answers

Question # 1

Which one of these statements is TRUE about code running on final hardware without a debugger attached?


It must start executing from RAM


RAM must be initialized before reset


Exception handlers must execute from ROM or flash memory


It must not execute semihosting SVC or BKPT instructions

Question # 2

A deeply embedded real-time industrial control system is missing some hard real-time interrupt deadlines. Which of the following performance analysis techniques is the most suitable for identifying which routines are causing the problem?


Use an ETM instruction trace profiler, which outputs information about the program as it runs


Add some serial logging to the software, which outputs information about the program as it runs


Add a new interrupt handler, which is triggered off a timer, and dump information about the interrupted process


Use a JTAG sample-based profiler, which periodically halts the CPU, and dumps information about the interrupted process

Question # 3

In which of the following situations would you use a mutex to avoid synchronization problems?


A single-threaded application needs to manage two separate UART peripherals


Two independent threads running on a single processor both need to access a single UART


In a dual-core system, a UART is accessed by a single thread running on one of the processors


In a dual-core system, processor A needs to access UART A and processor B needs to access UART B

Question # 4

When using the Performance Monitoring Unit to count runtime events the counter registers are limited to 32-bits. How can more than 2A32 events be counted without significantly impacting the software performance?


Register an interrupt which is triggered when the counter overflows


Count the events using a 64-bit VFP register


Allow one event type to use concatenated counter registers


Poll the event counter, resetting it when the counter is close to overflowing

Question # 5

When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?


Writes dirty data cache lines to memory


Reloads dirty data cache lines from memory


Speculatively preloads data into the cache


Writes dirty data cache lines to memory and marks those lines as invalid

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